# Ultra96-v2 GPIO test

本篇主要紀錄使用ultra96-v2寫一個簡單的GPIO程式，包含以下功能：

* 按鈕MIO23觸發console(uart)輸出一行命令，並且LED(D3-D7)亮燈，同時MIO36/37/39/40按照預先規劃好的流程動作輸出時序

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## 環境

* 系統環境: ubuntu 18.04
* Xilinx版本: 2021.2&#x20;

***

## 操作流程

## A. XSA檔建立 / Vivado building

如果尚未建立基本的XSA供Vitis使用，請參考A項目

1. board file update

在create project若找不到ultra96的板子資訊，必須先更新或是把[board file](https://github.com/Avnet/bdf)放到對應路徑，才可以建立專案。

可以參考這篇([ultra 96 v2 board not available in vivado](https://support.xilinx.com/s/question/0D52E00006hpWTtSAM/ultra-96-v2-board-not-available-in-vivado?language=en_US))，不過bdf放的路徑要改在 \<your path>/Vivado/202x.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx

2. 以Ultral96-V2建立block diagram&#x20;

<figure><img src="https://community.element14.com/resized-image/__size/1280x720/__key/communityserver-blogs-components-weblogfiles/00-00-00-03-95/8206.JPG" alt=""><figcaption><p>在Vender欄位搜尋avnet.com並找到ultra96-v2的板子，進行下載更新</p></figcaption></figure>

3. systhises,implentment,（沒有pl external就不用設定io）&#x20;
4. bitstream,建立xsa

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## B. Vitis

1. 根據xsa建立platform project
2. 整體流程可參考 hackster.io [這篇](https://www.hackster.io/BryanF/ultra96-v2-vitis-2020-2-hello-world-from-arm-a53-2d952a)，比較需要注意的是設定standalone BSP時A53的stdin,stdout要設定uart1，否則console會看不到任何訊息\
   ![](https://hackster.imgix.net/uploads/attachments/1289330/image_7j3L4DO7gN.png)![](https://hackster.imgix.net/uploads/attachments/1289331/image_J8cfhdWAuY.png)
3. 設定好之後對platform project,build project&#x20;
4. 確認都沒問題之後，建立appilcation project&#x20;
5. 選擇剛剛建立好的platform project作為基底，並且選你要使用的core&#x20;
6. 選擇hello world project產生模板，並且直接build project&#x20;
7. 檢查switch是否使用jtag模式，檢查uart連接的pin腳，並且上電開機\
   ![](https://hackster.imgix.net/uploads/attachments/1290275/image_RXwHPazifE.png)<br>

***

## C. Verilog Module

* 有時候會想快速的寫一個小module做測試，但又不想create IP package，可以將add verilog，再拖曳到block design，這樣就可以快速地進行測試。
* Axi module可以參考[這篇](https://gist.github.com/whosyourdadd/d7edf3a2bc79a2dc3ecbb9f2604d1423)的做法，裡面包含
  * [**LaserAXI\_Wapper.v**](https://gist.github.com/whosyourdadd/d7edf3a2bc79a2dc3ecbb9f2604d1423#file-laseraxi_wapper-v) : 用來跟外部PS Side連接
  * [**LasrCnt\_fstate.v**](https://gist.github.com/whosyourdadd/d7edf3a2bc79a2dc3ecbb9f2604d1423#file-lasrcnt_fstate-v)      : 主要是自己做的module
  * [**Xilinx\_AxiGpioTest.c**](https://gist.github.com/whosyourdadd/d7edf3a2bc79a2dc3ecbb9f2604d1423#file-xilinx_axigpiotest-c) : 放在vitis project，讓PS side可以控制

本篇參考

* [Ultra96-V2 Vitis 2020.2 Hello World from ARM A53](https://www.hackster.io/BryanF/ultra96-v2-vitis-2020-2-hello-world-from-arm-a53-2d952a)


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